Experimental validation build Results use a simplified input-circuit model and may contain numerical or modeling errors. Verify critical conclusions with measurements or detailed circuit simulation.
Ready
WARNING: ADC Clipping Detected! Signal voltage exceeded range [0V, Vref].
Dominant limiter Awaiting calculation The ENOB diagnosis will appear after the first simulation.
Single Point Numeric Results
Metric Value Equivalent Comment
Main result
-- bit -- dB Primary loss value for this operating point.
-- bit -- dB Resolution equivalent derived from measured SINAD.
-- dB THD Harmonic content relative to the fundamental.
-- -- LSB Analog sample undercharge shown with LSB equivalent.
Spectrum and residual
-- dB Target Ideal SINAD target for the selected nominal bit depth.
-- Peak Peak residual after removing the best-fit fundamental.
-- RMS RMS residual after the startup samples are discarded.
Loss decomposition
-- -- dB Linear C0G and ideal measurement; shows quantization, FFT and record limits.
-- -- dB Additional loss from nonlinear capacitance with ideal measurement of Vext.
-- -- dB Additional loss from sample undercharge on a linear capacitor.
-- -- dB Total extra circuit loss above the baseline floor.
-- -- dB Non-additive part: combined minus C(V) only minus settling only.
Time Domain Waveforms Transient Process
ENOB Error View Residual in LSB
Spectral Analysis (FFT Spectrum)
Nonlinear Capacitance C(V) Profile
Parametric Sweep Settings
Y Range Ω
X Range Hz
Safe Operating Regions (ENOB Loss Heatmap)
MLCC Component Database
Part Number Mfr Nominal Cap Rated V Dielectric Size Action
C(V) Bias Characteristics Comparison
Model reference

Methodology and Model Definition

Electrical object, equations, calculated metrics and explicit limits of the simulation.

01

Model overview

The tool models an external RC network connected to a switched-capacitor ADC input. Its purpose is engineering screening: estimate how voltage-dependent capacitance and incomplete acquisition affect spectral quality and effective resolution.

Scope: deterministic time-domain simulation of the input network. The result is not a transistor-level ADC model and not a complete physical model of a ferroelectric dielectric.
02

Circuit and observed signals

VinIdeal source waveform with amplitude, frequency and DC offset.
VextVoltage on the external nonlinear capacitor.
VshVoltage acquired by the internal sample-and-hold capacitor.
TacqTime during which the sampling switch is closed.
fsSampling rate; the sampling period is Ts = 1/fs.
03

Voltage-dependent capacitance C(V)

The external capacitor is represented by a differential capacitance evaluated at the current capacitor voltage. Generic C0G is constant; X7R/X5R and catalog presets reduce capacitance as the absolute applied voltage increases.

dVext/dt = Iext / Cext(Vext)

This is a quasi-static engineering approximation. Frequency dispersion, dielectric absorption, thermal effects and polarization history are intentionally outside the current model.

04

Acquisition settling

When the switch closes, Csh charges through Rsw while the external RC node is also moving. The settling metric is measured at the end of acquisition:

esettling[n] = Vext[n] - Vsh[n]

The table reports the peak absolute error both as voltage and as an equivalent number of LSB. A very large LSB number may still correspond to an ordinary analog voltage when a 24-bit scale is selected.

05

SINAD, effective ENOB and ENOB loss

SINAD compares the fundamental power with all remaining noise and distortion power in the analyzed spectrum.

SINAD = 10 log10(Pfund / Pnoise+dist)
ENOB = (SINAD - 1.76) / 6.02
ENOB loss = Nbits - ENOB

ENOB is a compact system metric. It does not identify the physical source of the loss; use the ablation rows and direct spectral metrics for diagnosis.

06

Total harmonic distortion

THD = 10 log10((PH2 + ... + PH10) / Pfund)

THD isolates energy at harmonic frequencies. More negative values indicate lower harmonic distortion. It is the direct metric for studying the nonlinear C(V) mechanism.

07

Residual error

A least-squares sine, cosine and DC model is fitted to the reconstructed samples. The residual is the sample sequence left after removing that best-fit fundamental.

r[n] = VADC[n] - Vfit[n]

Peak residual is useful for locating worst-case excursions; RMS residual is more representative of total error energy.

08

Loss decomposition by ablation

Baseline floorLinear C0G and ideal observation of Vext. Includes quantization, FFT and finite-record limitations.
C(V) onlyNonlinear external capacitance with ideal observation of Vext.
Settling onlyLinear external capacitor with the real switched acquisition path.
Combined extraFull model loss above the baseline floor.
InteractionCombined extra minus the separate C(V) and settling contributions. A non-zero value means the effects are not additive.
09

Numerical method and FFT

  • Semi-implicit integration is used for interactive calculations; Radau is available for high-accuracy verification.
  • The single-point analysis uses 1024 samples.
  • A four-term Blackman-Harris window reduces spectral leakage.
  • The fundamental and harmonic powers are integrated across the main-lobe bins.
  • Initial samples are excluded from peak settling and residual diagnostics.
10

Assumptions and limits

  • This is an experimental validation build; numerical and modeling errors are possible.
  • The source is ideal and has no output noise or harmonic distortion.
  • Rsw and Csh are fixed lumped parameters.
  • Comparator noise, reference noise, jitter, DNL and INL are not modeled.
  • The MLCC model is quasi-static and component presets are engineering fits, not guaranteed production limits.
  • Low-frequency FFT results require enough observed periods; short records can dominate the baseline floor.
Interpretation rule: use the tool to compare design directions and identify dominant mechanisms. Validate final hardware with component-specific data, measurement or detailed circuit simulation.
Project details

About the Project & Author

Background information, social links, and related publications.

01

Author Profile

Boris Kuznetsov is a Professor and Electronics Engineer specializing in precision measurement systems and embedded electronics. His work focuses on analog and mixed-signal circuit design, high-speed PCB design, digital signal processing, and instrumentation systems. He is also the creator of the YouTube channel @High_SNR_Channel, where he shares educational content on electronics, circuit design, and hardware development.

02

Official Profiles & Socials

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Contacts

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